STTM devices are non-volatile memory devices that utilize a phenomenon known as tunneling magnetoresistance (TMR). For a structure including two ferromagnetic layers separated by a thin insulating tunnel layer, it is more likely that electrons will tunnel through the tunnel layer when magnetizations of the two magnetic layers are in a parallel orientation than if they are not (non-parallel or antiparallel orientation). As such, an MTJ can be switched between two states of electrical resistance, one state having a low resistance and one state with a high resistance.
For an STTM device, current-induced magnetization switching is used to set the bit states. Polarization states of one ferromagnetic layer are switched relative to a fixed polarization of the second ferromagnetic layer via the spin transfer torque phenomenon, enabling states of the MTJ to be set by application of current. Upon passing a current through the fixed magnetic layer, angular momentum (spin) of the electrons is polarized along the direction of the magnetization of the fixed layer. These spin polarized electrons transfer their spin angular momentum to the magnetization of the free layer and cause it to precess. As such, the magnetization of the free magnetic layer can be switched by a pulse of current (e.g., in about 1 nano-second) exceeding a certain critical value with magnetization of the fixed magnetic layer remaining unchanged as long as the current pulse is below a higher threshold attributable to a different geometry, an adjacent pinning layer, different coercivity (Hc), etc.
The critical value of current required for switching magnetization of the free layer, referred to herein as the “critical current,” is a factor impacting the dimensions of a transistor coupled to the STTM device with larger critical currents requiring larger transistors, resulting in a larger footprint for a 1T-1 STTM element cell size, higher power consumption, etc. For STTM array capacity and power consumption to be competitive with other memory technologies, such as DRAM, a reduction in critical current is advantageous.